This invention relates generally to instruction set computing. In particular the invention relates to a method of executing an instruction set, and an execution processor for executing the instruction set.
Reduced instruction set computing (RISC) processors typically have a fixed bit-width instruction size. Common sizes are 16-bits and 32-bits. 32-bits give flexibility in expressing instructions and operands but at the expense of typically larger code size than the 16-bit instruction sets.
A problem with the short (16-bit) instruction sets is that they have a restricted number of bits for expressing operands. Some processors (for example those operating the reduced instruction set computer architecture MIPS) make use of prefixes. A prefix is an instruction which is associated with another instruction. A prefix contains the same number of bits as the instruction with which it is associated. For example, the MIPS architecture uses short instructions each having 16 bits. Both an MIPS prefix and the MIPS instruction with which it is associated have 16 bits. Generally, a prefix extends the operand of the instruction with which it is associated.
Prefixes have been used to signify that an operand in an instruction is to be interpreted as having the same meaning but in a different location in the instruction. In a simplified example, FIG. 1a illustrates an instruction in which operand A is in location 1, operand B is in location 2, operand C is in location 3, and operand D is in location 4 of an instruction. FIG. 1b illustrates a prefix which precedes the instruction of FIG. 1a and indicates that the operands in locations 1 and 3 of the instruction are to be interchanged. FIG. 1c illustrates the interpretation that the executing processor is left with of the instruction of FIG. 1a as a result of the prefix of FIG. 1b. The operands in locations 1 and 3 have been interchanged. Now operand C is in location 1, operand B in location 2, operand A in location 3, and operand D in location 4. This example is a simplified illustration. In a real situation the prefix would be used to carry out other functions as well as indicating that the operands in locations 1 and 3 of the instruction are to be interchanged.
Prefixes have been used to increase the number of instruction fields available, and to increase the number of bits in the instruction fields of the instruction with which the prefix is associated. For example, U.S. Pat. No. 6,651,160 describes a method of extending the number of addressable registers. Generally MIPS instructions provide 3 bits for each register address. U.S. Pat. No. 6,651,160 discloses 5-bit register addresses. The main instruction includes 3 of the 5 bits of each address, and the prefix associated with the main instruction includes the other 2 of the 5 bits of each address. Full 5-bit register addresses are therefore addressable by the combination of the main instruction and its associated prefix.
Although U.S. Pat. No. 6,651,160 enables 5-bit register addresses to be addressable using the main instruction and its associated prefix, it does not reduce the size of the overall instruction set because 5 bits are still required to describe a 5 bit register address.
There is therefore a need for a method of executing a reduced instruction set which enables information to be conveyed more efficiently by the reduced instruction set.